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markpsu
USA
67 Posts |
 Posted - 05 May 2020 : 01:52:44
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I have a design with a ton of stitching via's that I need to be masked over, there are other via's with through hole components that need to have the mask keep out as usual. The plot for the mask layer doesn't seem to have an obvious tickbox to use to make the mask only apply to certain via's (and not the stitching via's). In the past when I've encountered this I just created shapes over the through-hole via's and turned off the via's on the mask plots.
On this design there are too many to do manually. I see I can tag via's as testland so maybe I could tag my through-hole's this way and only plot them but these are not testlands so I'm not sure if there is a better way. Does anyone have suggestions for this?
Thanks, Mark
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Iain Wilkie
United Kingdom
1010 Posts |
Posted - 05 May 2020 : 09:07:42
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Under the Design Technology/Layer Types you can pick and choose if vias and other pad types can be selected to have resist or not.
Your through holes for components you mention will probably not be vias but all layer symbol pads so can be set up differntly.
Always best to have your mask layers set up in the layers so you can "see" what your mask outputs look like with the normal PCB editor screen
Iain
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edrees
United Kingdom
766 Posts |
Posted - 05 May 2020 : 09:25:27
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As Iain says EPC knows the difference between thru plated (component) pads and vias. However now (obviously!) all vias (including signal track vias) will be tented over with resist.
There is also a Gerber plot "tick" box settings for "Normal Vias" (under default solder resist plot =>Settings, Pads only plot) that you could try depending on complexity of your resist layers.
Check your Gerber plots afterwards with an independent viewer to make sure you have what you expect. |
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markpsu
USA
67 Posts |
Posted - 05 May 2020 : 19:15:55
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You are correct Easy PC does know between the stitching via's and the through-hole via's when plotting the mask. That was a nice surprise.
Now, I have a new problem. When exporting the copper layers the holes for all the stitching via's and other via's connected to the ground copper pour area do not show up. The holes for the through via's (not connected to ground) do show on the gerber copper layers.
This is causing a problem when importing into simulation software as some layers are missing the via. Is there a checkbox I'm missing? |
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edrees
United Kingdom
766 Posts |
Posted - 05 May 2020 : 19:26:27
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| Hi are you 100% sure that the stitching bias are actually connected to Ground. Does the drill table or drill file list all the stitching vias? Make the hole size for the stitching vias unique may help identify them. |
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edrees
United Kingdom
766 Posts |
Posted - 05 May 2020 : 19:28:03
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quote:
Originally posted by edrees
Hi are you 100% sure that the stitching vias are actually connected to Ground. Does the drill table or drill file list all the stitching vias? Make the hole size for the stitching vias unique may help identify them.
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edrees
United Kingdom
766 Posts |
Posted - 05 May 2020 : 19:30:05
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[quote]Originally posted by edrees
[quote]Originally posted by edrees
Hi are you 100% sure that the stitching vias are actually connected to Ground. Does the drill table or drill file list all the stitching vias? Make the hole size for the stitching vias unique may help identify them.
May also be due to a plot setting regarding a setting "fill in drill holes". |
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edrees
United Kingdom
766 Posts |
Posted - 06 May 2020 : 10:08:46
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Ummmmm!
Just tried this on a "scrap" pcb design. With both "Fill Plated and Fill Unplated boxes unticked, (Gerber plot settings) the stitching vias (to Gnd flood) on the copper layer appear "filled" (i.e. invisible) whereas the other "signal" vias do have drill holes. However, so do the component pads (that are connected to the flood area)
The Resist Layer shows the drill holes for stitching vias, Signal (non- tented) vias and component pads.
The PDF plot outputs are similar to the Gerber plots and the 3D viewer (when resist mask is switched off).
Looks like a drill hole for a via or pad connected to a flood copper area will not "show up" on plots, -but the Solder Resist mask will! Doesn't affect the pcb manufacturing process though.
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Edited by - edrees on 06 May 2020 10:29:59 |
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markpsu
USA
67 Posts |
Posted - 06 May 2020 : 13:39:31
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Yes, I spent yesterday trying to make this happen but determined it's not possible. Eventually I was smart enough to look back at similar designs that have been produced and they had the same condition.
So, I think this is how it's meant to be although not seeing holes that are there in real life is a little strange. I'm having the board crash in simulation so I thought this might be the cause, but since similar boards have been simulated it must not be for this reason. We've actually had many boards in the past built with this condition so it seems I've been chasing a problem that might not exist.
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edrees
United Kingdom
766 Posts |
Posted - 07 May 2020 : 09:14:58
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I previously stated,-
quote:
Looks like a drill hole for a via or pad connected to a flood copper area will not "show up" on plots, -but the Solder Resist mask will! Doesn't affect the pcb manufacturing process though.
This is true for Production pcbs where the (majority of) holes are drilled at the pre-etch stage, but a PITA with home brew pcbs where the holes are drilled post etch where the etched hole helps to identify the pad position and self-center the drill bit. I'll ask Support to investigate a fix!
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Peter Johnson
United Kingdom
490 Posts |
Posted - 07 May 2020 : 12:55:24
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| I'm pretty certain that I know what's going on here. Take a look in the help index for the entry on 'Drill Backoff Check'. Obviously without seeing the particular design, I can't be sure, but the posts so far would fit this as a reason for the behaviour. |
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edrees
United Kingdom
766 Posts |
Posted - 07 May 2020 : 13:06:00
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Thanks Peter, I think you're correct.
Of course for a fat track one could reduce the width to comply with the "Backoff Check" rule, -but with a flood area this is impossible. Cheers! |
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Topic |
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Via's & mask layer