Hello, I was wondering if anyone has any experience with the layout when adding a Cat6a Ethernet jack to the PCB?
Of course you will want to keep the differential pairs the same length and as short as possible. I'm also being told that you may need to do some filtering with some additional capacitance compensation within the routing. Has anyone had experience with this that they could share?
Normally the datasheet for the chip that connects to the ethernet jack (PHY) will give any real relevant info, but normally it is a simple matter of ensuring the diff lines are impedance balanced, short as possible and the same length. Ensure a good unbroken ground plane.
Thanks, I looked at a few datasheets and see the general differential routing guidance along with the "Bob Smith" termination. I was thinking some additional filtering would be needed for the higher speed Cat6a Ethernet jacks.
High speed Ethernet jack layout
Posted - 13 Oct 2022 : 16:51:23
